Decoding-Complexity-Aware HEVC Encoding Using a Complexity-Rate-Distortion Model
Kodikara Arachchi, Hemantha
Institute of Electrical and Electronics Engineers (IEEE)
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The energy consumption of consumer electronic (CE) devices during media playback is inexorably linked to the computational complexity of decoding compressed video. Reducing a CE device's the energy consumption is therefore becoming ever more challenging with the increasing video resolutions and the complexity of the video coding algorithms. To this end, this paper proposes a framework that alters the video bit stream to reduce the decoding complexity and simultaneously limits the impact on the coding efficiency. In this context, this paper first performs an analysis to determine the tradeoff between the decoding complexity, video quality, and bit rate with respect to a reference decoder implementation on a general purpose processor architecture. Thereafter, a novel generic decoding complexity-aware video coding algorithm is proposed to generate decoding complexity-rate-distortion optimized High Efficiency Video Coding (HEVC) bit streams. The experimental results reveal that the bit streams generated by the proposed algorithm achieve 29.43% and 13.22% decoding complexity reductions for a similar video quality with minimal coding efficiency impact compared to the state-of-the-art approaches when applied to the HM16.0 and openHEVC decoder implementations, respectively. In addition, analysis of the energy consumption behavior for the same scenarios reveal up to 20% energy consumption reductions while achieving a similar video quality to that of HM 16.0 encoded HEVC bit streams.
IEEE Transactions on Consumer Electronics;
Mallikarachchi, T., Talagala, D.S., Arachchi, H.K. and Fernando, A. (2018) 'Decoding-Complexity-Aware HEVC Encoding Using a Complexity–Rate–Distortion Model', IEEE Transactions on Consumer Electronics, 64(1), pp.35-43. DOI: 10.1109/TCE.2018.2810479.
Article published in IEEE Transactions on Consumer Electronics on 02 March 2018, available at: https://doi.org/10.1109/TCE.2018.2810479.
Sponsored by: IEEE Circuits and Systems Society
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